module TimerPenaltyLogic(
    input clk_10Hz,
    input rst_n,
    input start,
    input key_correct,
    input key_wrong,
    input game_done,
    output reg [11:0] time_used,
    output reg [7:0] time_penalty,
    output reg game_running
);

    always @(posedge clk_10Hz or negedge rst_n) begin
        if (!rst_n) begin
            time_used <= 0;
            time_penalty <= 0;
            game_running <= 0;
        end else if (start) begin
            time_used <= 0;
            time_penalty <= 0;
            game_running <= 1;
        end else if (game_running && !game_done) begin
            time_used <= time_used + 1;   // 单位0.1秒
            if (key_wrong && time_penalty < 8'd255)
                time_penalty <= time_penalty + 1;  // 每错一次扣0.1秒
        end else if (game_done) begin
            game_running <= 0;
        end
    end

endmodule
